This invention relates generally to semiconductor circuits providing electrostatic discharge (ESD) protection, and more specifically, to a distributed ESD protection scheme.
An integrated circuit may be subject to an Electrostatic Discharge (ESD) event in the manufacturing process, during assembly and testing, or in the ultimate system application. In conventional integrated circuit (IC) ESD protection schemes, special clamp circuits are often used to shunt ESD current between the power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) clamp circuit, typically consists of three functional elements; a Resistor-Capacitor (RC) transient detector circuit, an intermediate buffer circuit, and a large MOSFET transistor, which serves as the primary ESD current shunting device. Active MOSFET clamp circuits may be employed in networks distributed along the IC power buses to provide robust and consistent ESD protection for multiple Input/Output (I/O) pads. Multiple embodiments of such networks are shown in U.S. Pat. No. 6,385,021 entitled xe2x80x9cElectrostatic Discharge (ESD) Protection Circuitxe2x80x9d and assigned to the assignee hereof.
FIG. 1 illustrates one such distributed ESD network 1000 in an IC to protect multiple I/O circuits 1030-1032. While only three I/O circuits are shown in this schematic, in a typical implementation the distributed network would encompass a much larger bank of I/O circuits. I/O circuit 1032 includes an external connection pad 1050 that is coupled between the VSS bus 1042 and the VDD bus 1044. A diode 1052 has an anode connected to the VSS bus 1042 and a cathode connected to the I/O pad 1050. A diode 1053 has an anode connected to the I/O pad and a cathode connected to the VDD bus 1044. In one example of ESD network 1000, the diode 1053 is formed as a P+ active in NWELL diode and the diode 1052 is formed as a N+ active in P-substrate diode. A clamp N-channel MOSFET (NMOSFET) 1054 is connected between the VSS bus 1042 and the VDD bus 1044. The gate of clamp NMOSFET 1054 is connected to a Trigger bus 1046. Not shown in I/O circuit 1032 is the circuitry desired to be protected, such as for example P-channel MOSFET (PMOSFET) and N-channel (NMOSFET) output drivers, and other circuit components typically required for I/O operation. I/O circuits 1030 and 1031, each identical to I/O circuit 1032, are also shown in FIG. 1. A remote trigger circuit 1040 contains an RC transient detector circuit 1063 and a buffer circuit 1064. RC transient detector circuit 1063 includes a capacitor 1061 connected between the VSS bus 1042 and a node 1065, and a resistor 1062 connected between this same node and the VDD bus 1044. Buffer circuit 1064 may, for example, contain a series of three series-connected CMOS inverter stages, not shown, between the input at node 1065, and the output to the Trigger bus 1046 at node 1066. Each inverter stage typically has a PMOSFET with its source connected to the VDD bus 1044 and a NMOSFET with its source connected to the VSS bus 1042.
Three buses are shown in FIG. 1, a VSS bus 1042, a VDD bus 1044, and a Trigger bus 1046. These buses are typically routed around all or part of the IC periphery, to serve the I/O circuits normally placed in this region. A series of incremental bus resistors, each labeled R1, is shown on the VDD bus 1044 between two adjacent I/O circuits, or an I/O circuit and an adjacent remote trigger circuit. Each resistor represents the distributed parasitic metal resistance for that segment of the VDD bus 1044 between two adjacent circuits. The bus length from the physical center of one such circuit to the physical center of the adjacent circuit may be used in making these resistance calculations. While these resistors are all shown with the label R1, it should be understood that these resistance values often vary considerably in magnitude as the physical spacing between I/O circuits, or between an I/O circuit and a remote trigger circuit, is varied. Similarly variable incremental bus resistors, each labeled R2, are shown on the Trigger bus 1046. Incremental bus resistors may also be shown on the VSS bus 1042, but are not included in FIG. 1 in order to clarify the schematic. Note that in a typical IC application, additional I/O circuits and additional incremental bus resistors (R1, R2) may be added to the ESD protection network, as indicated by the dots placed to the left and right of the elements shown in FIG. 1.
Integrated circuits are often most susceptible to damage during positive ESD events coupled onto an I/O pad referenced to grounded VSS. The primary response of ESD network 1000 to this event applied to I/O pad 1050 in FIG. 1 is as follows. Diode 1053 forward biases as the I/O pad voltage very quickly ramps well above 0.7V. This then produces a rapid voltage increase over time (dV/dt), or voltage slew rate on the VDD bus 1044. The RC transient detector circuit 1063 is one type of voltage transient detector circuit or voltage slew rate sensor circuit. In response to the very rapid ESD-induced dV/dt on the VDD Bus 1044, transient detector circuit 1063 initially holds node 1065 well below VDD. The buffer circuit 1064 senses this input low and outputs an inverted and amplified signal that drives the Trigger bus 1046 to VDD. This turns on the multiple clamp NMOSFETs 1054 distributed in each I/O circuit. Note that since the remote trigger circuit 1040 is driving only gates of the distributed clamp NMOSFETs 1054, the resulting current routed onto the Trigger bus 1046 is very small. Once turned on, this cumulative network of clamp NMOSFETs acts as a low resistance shunt between the VDD bus 1044 and the VSS bus 1042. The clamp NMOSFETs will remain conductive for a period of time that is determined by the RC time constant of the transient detector circuit 1063. This time constant should be set to exceed the typical duration of an ESD event (200-500 nanoseconds), while short enough to avoid false triggering of the clamp NMOSFETs during normal ramp up of the VDD bus. The VDD ramp up during normal IC operation typically requires 1-5 microseconds.
As described above, transient detector circuits respond to an applied ESD event by sensing a rapid voltage increase over time (dV/dt) on the VDD bus. It should be pointed out that another type of ESD detector circuit, a voltage threshold detector circuit, exists in the prior art. Voltage threshold detector circuits respond to an applied ESD event by sensing that a predetermined voltage threshold on the VDD bus has been exceeded. If this threshold is not exceeded, then the clamp NMOSFETs remain nonconductive.
During the ESD event described above, the I/O pad 1050 voltage rises to a peak level set by the sum of the voltage drops as the peak current of the applied ESD event flows through the intended dissipation paths. In the industry standard 200V Machine Model ESD event, the peak current forced through the IC may reach about 3.8A. In order to protect fragile elements in I/O circuit 1032, the ESD clamp network must typically prevent the I/O pad 1050 voltage from rising above a critical voltage failure threshold, which typically varies in a range from 6-10V, depending on process technology and output buffer configuration. Assuming, for example, an 8.0V failure threshold for the I/O circuit and a 3.8A peak ESD current, the net resistance through the entire dissipation path may not exceed about 2.1 ohms. Such an ESD path requires large active devices and robust interconnections between these devices.
U.S. Pat. No. 6,385,021, from which FIG. 1 is based, teaches the benefit of distributing small clamp NMOSFETs 1054 in each of the I/O circuits, as opposed to less frequent placement of larger clamp NMOSFETs along the power supply buses. This approach minimizes the impact of VDD bus resistance on ESD performance. When any I/O pad experiences a positive ESD event referenced to grounded VSS, the individual clamp NMOSFETs 1054, distributed in each I/O circuit, turn on in parallel. However, due to the resistance on the VDD bus, only the clamp NMOSFETs in the vicinity of the stressed pad, in both directions along the bus, tend to shunt the majority of the ESD current. The cumulative effect of the many individual small clamp NMOSFETs allows multiple devices to harmlessly dissipate very large ESD currents. In networks with much less frequent placement of large clamp NMOSFETs, I/O pads placed most distant from these clamps suffer reduced ESD performance due to increased current-times-resistance (IR) voltage drop from the stressed I/O pad to the large clamp NMOSFETs. Note that even in the distributed small clamp NMOSFET networks as illustrated in FIG. 1, large clamp NMOSFETs are still needed at any point where the VDD bus is broken or terminated, to adequately protect I/O pads near the end of that VDD bus segment. Without this large clamp NMOSFET, a stressed I/O pad at the end of a VDD bus segment will only be able to access clamp NMOSFETs in one direction along the VDD bus. This will translate into significantly reduced ESD performance. In a preferred configuration, the VDD bus forms a continuous ring around the IC so that the VDD bus is not terminated. With this configuration, the network of small clamp NMOSFETs in the I/O circuits can provide complete ESD protection.
U.S. Pat. No. 6,385,021 also teaches the benefit of placing all or part of the rail clamp trigger circuitry in a location remote from the I/O circuits, driving the Trigger bus 1046 which gates each of the clamp NMOSFETs 1054 in a bank of I/O circuits. In many respects, this is preferable to the alternate approach of placing separate trigger circuits in each I/O circuit, to drive only the clamp NMOSFET located in that individual I/O circuit. This is because, in many chip designs, the I/O circuit is the most constrained portion of the IC periphery in terms of substrate or physical layout area. Reducing layout area in the I/O circuit often translates directly into smaller IC die size. RC transient detector circuits typically occupy a considerable layout area. Therefore it is more space efficient to share a single RC transient detector circuit 1063 among multiple clamp NMOSFETs in a bank of I/O circuits. The sizes of elements in buffer circuit 1064, on the other hand, are typically scaled depending on the total channel width of the clamp NMOSFETs that trigger circuit must drive. As taught in U.S. Pat. No. 6,385,021, elements of buffer circuit 1064 may be conveniently placed either in remote trigger circuit 40, in each individual I/O circuit 1032, or divided into portions and placed partly in the remote trigger circuit and partly in each I/O circuit.
It turns out that there are some limitations with the resulting ESD network, when placing the full buffer circuit 1064 in the remote trigger circuit 1040, as shown in FIG. 1. One limitation with this approach is that the maximum distance between any I/O pad and its closest remote trigger circuit 1040 is limited, due primarily to IR voltage drops along the VDD bus from a stressed I/O pad to the remote trigger circuit. This limitation can be best demonstrated by simulating an ESD event on the network with standard circuit simulation tools and analyzing the resulting nodal voltages. Assume the network of FIG. 1 is part of a large bank of I/O circuits and incremental bus resistors. Consider the case where I/O pad 1050 experiences a positive 3.8A peak current ESD event referenced to grounded VSS. Assume that the sizes of diode 1053 and clamp NMOSFET 1054 in each I/O circuit, and the magnitude of resistor R1 on the VDD bus, are adjusted so that the simulated voltage on I/O pad 1050 rises to a peak of 8.0V during this ESD event. At the peak ESD current level, the voltage drops across the diode 1053 and the parasitic interconnect resistances (not shown in FIG. 1) from this diode to the I/O pad and to the VDD bus typically sum to about 3.0V. Therefore the peak voltage on the VDD bus local to the stressed I/O pad is about 5.0 volts. ESD current will be routed along the VDD bus in both directions away from the stressed pad with the majority of the current shunted through the distributed rail clamp NMOSFETs 1054 within 1-2 ohms of VDD bus resistance. Note that due to this current flow, the peak VDD bus voltage is found local to the stressed I/O pad, and drops off in both directions away from the stressed pad. In this example simulation, the peak VDD bus voltages local to I/O circuits 1031, 1030, and remote trigger circuit 1040 are 4.7V, 4.5V, and 4.3V, respectively. Therefore the drain terminals of the distributed clamp NMOSFETs will be biased to different voltage levels depending on the proximity to the stressed I/O pad. However, the gate terminals of the distributed clamp NMOSFETs will be biased to the same voltage level, since they are all driven by the remote trigger circuit 1040 via the Trigger bus 1046. It is important to note that the voltage level of the Trigger bus will be dependent on the proximity of the remote trigger circuit to the stressed I/O pad. When activated during an ESD event, the remote trigger circuit drives the Trigger bus to a voltage level equal to the VDD bus potential local to that trigger circuit, in this case 4.3V. Therefore, clamp NMOSFETs closer to the stressed I/O pad than the remote trigger circuit will have a gate-to-source voltage (Vgs) less than the drain-to-source voltage (Vds), while clamp NMOSFETs more distant from the stressed I/O pad than the remote trigger circuit will have Vgs greater than Vds. Clearly, when the stressed I/O pad is located greater distances away from the remote trigger circuit than in the case described above, the IR drop along the VDD bus leads to further reductions in the resulting voltage level of the Trigger bus. It is very important to note that the voltage level on the Trigger bus is critical to ESD network performance. The drain-to-source on-resistance of the clamp NMOSFETs is approximately inversely proportional to Vgs, under these bias conditions. Therefore I/O pads most distant from remote trigger circuits will suffer the worst ESD performance.
Another limitation with the ESD protection circuit described in FIG. 1 is that the Trigger bus 1046 is subject to having voltage contention issues when there are multiple remote trigger circuits 1040 placed in parallel along the VDD bus 1044. Two trigger circuits located different distances from a stressed I/O pad would each attempt to drive the Trigger bus to different voltage levels. This could cause serious bus voltage contention problems. One solution to address the voltage contention issues is to segment the VDD bus and place only one remote trigger circuit 1040 per VDD bus segment. Therefore, the maximum length of a VDD bus segment is limited, both to minimize IR drop from a stressed I/O pad to a remote trigger circuit, and to a length which may be served by a single remote trigger circuit. In IC designs it may be very difficult to partition the VDD bus into such small segments. Thus there is a need for a new distributed rail clamp network with fewer limitations on the maximum length of the protected VDD bus.
The distributed rail clamp network described in FIG. 1 contains a plurality of individual, discrete, rail clamp NMOSFETs placed in each I/O circuit. This scheme can be a limitation in designs where the physical spacing between I/O circuits is large or varies considerably around the periphery of the IC. For example, many ICs utilize I/O circuits of a fixed physical height and width, taken from a standard cell design library. However, the spacing or gap between I/O circuits in a given IC can vary depending on the number of I/Os required and the physical IC core size. Therefore, in many IC designs, there are significant gaps between I/O circuits. In addition, it is common to increase the spacing between I/O circuits near the IC corners, to accommodate radial bond wire sweeps in the package. There is also typically a large gap between I/O circuits as the metal buses are routed around the IC corners.
From a distributed ESD network design point of view, any gap between I/O circuits, or any variability in gaps between I/O circuits has a negative impact on ESD performance. For example, an I/O pad in the center of a bank of widely spaced I/O circuits would suffer decreased ESD performance to VSS as compared to an I/O pad in a bank with physically abutted I/O circuits. This is due to the fact that, in a network of identically sized small rail clamp NMOSFETs distributed along a resistive power bus, the I/O pad ESD performance is very sensitive to varying incremental bus resistances R1 between the clamp NMOSFETs. One approach taught in U.S. Pat. No. 6,385,021 to minimize the impact of this problem, is to augment the clamp NMOSFETs in the I/O circuits with additional clamp NMOSFETs placed in spacer cells between I/O circuits. While this approach is effective at minimizing the worst case incremental VDD bus resistance R1 between clamp NMOSFETs, it typically requires that a large number of unique spacer cells be designed and placed for each different spacing between I/O circuits. However, since it is preferred that ESD protection networks be constructed with a minimum number of simple, modular, and reusable ESD elements, this approach is not ideal. Therefore, when sizing clamp NMOSFETs in these distributed networks, the designer often simply assumes a single R1 value for incremental bus resistors between all I/O circuits based on the worst case actual pad to pad spacing in the IC. This worst-case spacing is often twice the minimum pad-to-pad spacing measured if all the I/O circuits were abutted. A disadvantage of this approach is that the resulting required clamp NMOSFET channel width is then about twice the width that would have been required if all the I/O circuits were indeed abutted. For these reasons, there is a need for a new ESD network scheme which would utilize a minimum number of unique ESD elements, yet which would allow for minimum rail clamp NMOSFET channel widths in the region of each I/O circuit, and minimum variability in ESD performance from one I/O pad to the next, while allowing the maximum flexibility to place I/O circuits around the IC periphery with arbitrary spacing.